1. Field of the Invention
The present invention relates to a semiconductor memory device that can operate at high speed.
2. Description of the Background Art
Recent computers are incorporated with a main memory and a cache memory. A dynamic random access memory (DRAM) or the like is generally used for the main memory. The dynamic random access memory having a large capacity is slow in operation. Therefore, for the purpose of temporarily storing a portion of data of the main memory and carrying out frequent access to a particular address speedily, a cache memory capable of high speed operation, but of small storage capacity, is used. A static random access memory (SRAM) or the like is generally used for the cache memory.
There is the case where data of a large amount is read out, modified, and written back in a system incorporating such a cache memory. For example, such a process includes the image data correction process and the like.
FIG. 16 is a schematic diagram to describe the operation of reading out data, modifying the data, and writing back the data.
Referring to FIG. 16, a main memory 506 has addresses M0-M13, and a cache memory 504 has addresses C0-C4. Here, it is assumed that the amount of data that can be stored in one of addresses C0-C4 of the cache memory 504 is equal to the amount of data that can be stored in one of addresses M0-M13 of the main memory 506.
The operation of sequentially reading out data stored in addresses M0-M13 of the main memory 506, modifying the data in a CPU 502, and then writing back the data into addresses M0-M13 of the main memory 506 will be described here.
At step S1, data stored in address M0 of the main memory 506 is copied into address C0 of the cache memory 504, and then read into the CPU 502. The CPU 502 outputs the modified data. In general, the modified data is temporarily stored in the cache memory 504. When there is no more empty region in the cache memory 504, the data in the cache memory 504 is transferred to the main memory 506. At the current point, the modified data is stored in address C0 of the cache memory 504, and not yet transferred to the main memory 506.
At steps S2-S5, the data in addresses M1-M4 of the main memory 506 are similarly copied into addresses C1-C4 of the cache memory 504. The CPU 502 provides respective modified data to the cache memory 504, whereby the data retained in addresses C1-C4 of the cache memory 504 are rewritten.
At this time point, there is no more empty region in the cache memory 504. In the subsequent process, data is read out from the main memory 506 into the cache memory 504 after the process of writing the modified data back into the main memory 506.
At step S6, the modified data stored in address C0 of the cache memory 504 is written back into address M0 of the main memory 506. At step S7, the data retained in address M5 of the main memory 506 is read into address C0 of the cache memory 504.
At step S8, the data stored in address C1 of the cache memory 504 is written back into address M1 of the main memory 506. At step S9, the data retained in address M6 of the main memory 506 is read into address C1 of the cache memory 504.
Thereafter, writing back data from the cache memory 504 into the main memory 506, and reading out data from the main memory 506 into the cache memory 504 are carried out similarly. In this case, data readout and data writing are carried out alternately in the main memory 506 with respect to continuous read and write addresses apart from each other by a constant address.
FIG. 17 shows a schematic structure of a conventional semiconductor memory device.
Referring to FIG. 17, a conventional semiconductor memory device 511 receives control signals CS, RAS, CAS, WE, an address signal ADR, and a bank address signal BANK from a memory control device 519 incorporated in a computer system or the like to transfer data DATA.
Semiconductor memory device 511 includes a control circuit 512 receiving control signals CS, RAS, CAS, and WE, address signal ADR and bank address signal BANK to output a row address RA and a column address CA, and also a data input signal DIN according to data DATA, or provides data DATA to memory control device 519 according to a data output signal DOUT read out, a row decoder 513, a column decoder 514, an amplify circuit band 516, and a memory cell array 517.
Row decoder 513 renders active one of a plurality of word lines WL according to an externally specified row address RA. Column decoder 514 renders active one of a plurality of column select lines CSL according to an externally specified column address CA. A memory cell located at the crossing between activated word line WL and column select line CSL is selected from the memory cell array.
An address signal ADR specifying a word line is provided together with an active command ACT. This address signal ADR is recognized as row address RA. An address signal ADR specifying a column select line is applied together with a read command RD or a write command WRT. This address signal ADR is recognized as column address CA. Read command RD and write command WRT designate reading and writing operations with respect to memory cells of respective specified addresses.
FIG. 18 is a circuit diagram showing a structure of a conventional memory cell array 517 of FIG. 17.
Referring to FIG. 18, each of memory cells Cell00-Cell21 is formed of a capacitor having one end coupled to a cell plate potential Vcp of a constant potential, and a transistor connected to the other end of the capacitor. The transistor is controlled by word line WL, and has the other end connected to a bit line BL or /BL. Sense amplifiers 24 and 44 are provided corresponding to the bit line pair of lines BL, /BL. Also corresponding to the bit line pair are provided transistors 22 and 42 equalizing the potentials of bit lines BL and /BL according to a signal BLEQ. Bit lines BL, /BL are connected to local IO lines LIO, /LIO via select gates 26 and 56 respectively controlled according to column select signals CSL0 and CSL1.
Local IO lines LIO, /LIO are connected to global IO lines GIO, /GIO by a gate circuit 60 rendered conductive by a signal IOSW0.
A read amplifier 64 and a write data drive circuit 62 are connected to global IO lines GIO, /GIO. Read amplifier 64 amplifies the potentials of global IO lines GIO, /GIO to output a signal DOUT. Write data drive circuit 62 functions to drive complementarily global IO lines GIO, /GIO according to a data input signal DIN.
Referring to FIG. 16 again, data is read out from address M4 of the main memory into address C4 of the cache memory on a computer having a cache memory (S5). The CPU modifies the read out data. The modified data is temporarily retained in the cache memory. Then, data is written back from address C0 of the cache memory into address M0 of the main memory (S6). Consider the case where data is read out from address M5 of the main memory into address C0 of the cache memory (S7).
FIG. 19 is an operation waveform diagram to describe the case where access is effected to a main memory employing a synchronous semiconductor memory device (SDRAM).
It is assumed that addresses M0, M4 and M5 of the main memory correspond to (row address RA, column address CA)=(000, 000), (001, 000), (001, 001), respectively, in FIG. 19. It is assumed that bank addresses BANK are all 0. Addresses M0, M4 and M5 correspond to memory cells Cell00, Cell10, and Cell11, respectively, in FIG. 18.
Referring to FIG. 19, command ACT and address xe2x80x9c001xe2x80x9d are input at time T1. Signal BLEQ is pulled down to an L level, and equalization of the bit line pair is canceled. Then, word line WL1 attains an H level.
Memory cells Cell10 and Cell11 of FIG. 18 are selected. The data stored in these memory cells are transmitted onto bit line BL. Then, a sense amplifier activation signal S0 is pulled up to an H level, whereby the potential difference of the bit line pair is amplified. In the case where the data stored in memory cells Cell10 and Cell11 are xe2x80x9cHxe2x80x9d and xe2x80x9cLxe2x80x9d, respectively, bit line BL0 is driven to an H level whereas bit line BL1 is driven to an L level. Although not depicted in the waveform diagram, bit line /BL takes a value complementary to the value of bit line BL.
At time T2, read command RD and address xe2x80x9c000xe2x80x9d are input, whereby column select line CSL0 is selected. The transistor of gate circuit 26 is rendered conductive, whereby the potential of bit line BL0 is transmitted via this transistor. As a result, local IO line LIO attains an H level. Then, signal IOSW0 attains an H level, whereby the transistor of gate circuit 60 is rendered conductive. Global IO line GIO attains an H level via this conducting transistor. Then, read amplifier 64 amplifies the same to output a data output signal DOUT.
Although the data in the cache memory is rewritten, the rewritten data is not yet transferred to the main memory.
At time T3, a precharge command PRE is input. In response, the potential of word line WL1 attains an L level, whereby the memory cells are disconnected from the bit lines. Then, signal BLEQ attains an H level, and sense amplifier activation signal S0 attains an L level. The sense amplifiers rendered inactive, and the bit line pair is equalized.
At time T4, active command ACT and address xe2x80x9c000xe2x80x9d are input. In response, signal BLEQ is pulled down to an L level, whereby equalization of the bit line pair is canceled. Word line WL0 is rendered active. In response, memory cells Cell00 and Cell01 are selected. The data retained in these memory cells are transmitted to corresponding bit lines, followed by operation of the sense amplifier. Bit lines BL0 and BL1 attain an L level and an H level, respectively, corresponding to the data stored in the memory cells.
At time T5, signals of an H level are input as data DATA with write command WRT and address xe2x80x9c000xe2x80x9d to write the data of address C0 in the cache memory back into memory cell Cell00.
In response, data input signal DIN attains an H level, whereby global IO line GIO is driven to an H level. Then, signal IOSW0 attains an H level, whereby local IO line LIO is pulled up to an H level. The level of column select line is H, whereby the H level of local IO line LIO is transmitted to data bit line BL0. Then, the data in memory cell Cell00 is rewritten into xe2x80x9cHxe2x80x9d.
At time T6, precharge command PRE is input, and word line WL0 is rendered inactive. Then, signal BLEQ and sense amplifier activation signal S0 attain an H level and an L level, respectively, whereby the sense amplifier is rendered inactive. The bit line pair is equalized.
At time T7, active command ACT and address xe2x80x9c001xe2x80x9d are input. Signal BLEQ attains an L level, and equalization of the bit line pair is canceled. Word line WL1 is rendered active.
At time T8, read command RD and address xe2x80x9c001xe2x80x9d are input, and column select line CSL1 is rendered active. In response, the transistor in gate circuit 56 conducts, whereby the potential of bit line BL1 is transmitted to local IO line LIO via the transistor. As a result, the potential of local IO line LIO attains an L level. Then, signal IOSW0 attains an H level. Global IO line GIO attains an L level via the transistor of gate circuit 60. Read amplifier 64 amplifies the potential of global IO line GIO to output data output signal DOUT of an L level.
When reading or writing is to be carried out with respect to memory cells connected to different word lines in the same bank, three commands are necessary to each cycle of reading and writing. More specifically, commands ACT, RD and PRE are required for a read cycle, whereas commands ACT, WRT and PRE are required for a write cycle. This operation will require three times the period of time than repeating readout from continuous addresses such as a burst read operation. Therefore, the effective transfer rate of data is greatly degraded.
Thus, in a computer incorporating a main memory such as a SDRAM of conventional structure, there was a problem that the effective transfer rate with respect to the main memory is extremely degraded when data of a great amount exceeding the capacity of the cache memory is read out, modified, and written back.
An object of the present invention is to provide a semiconductor memory device suited for a main memory that is not reduced in effective transfer rate even when data of a great amount exceeding the capacity of the cache memory is read out, modified, and written back.
According to an aspect of the present invention, a semiconductor memory device includes a plurality of memory cells, a plurality of word lines, a plurality of bit line pairs, a plurality of sense amplifiers, a data line pair, a plurality of first connection circuits, a plurality of data retain circuits, and a plurality of second connection circuits.
The plurality of memory cells are arranged in a matrix. The plurality of word lines are provided corresponding to respective rows of memory cells. The plurality of bit line pairs are provided corresponding to respective columns of memory cells. The plurality of sense amplifiers are provided corresponding to the plurality of bit line pairs, respectively. The data line pair is provided common to the plurality of bit line pairs to transfer stored data with respect to an external source. The plurality of first connection circuits selectively connect the plurality of bit line pairs to a data line pair according to an applied column address. The plurality of data retain circuits are provided corresponding to the plurality of bit line pairs, respectively. The plurality of second connection circuits connect the plurality of data retain circuits to the plurality of bit line pairs, respectively.
According to another aspect of the present invention, a semiconductor memory device includes a plurality of memory cell array blocks, a block decode circuit, and a select circuit.
Each memory cell array block includes a plurality of memory cells arranged in a matrix, a plurality of word lines each provided corresponding to a row of memory cells, a plurality of bit line pairs each provided corresponding to a column of memory cells, a plurality of sense amplifiers provided corresponding to a plurality of bit line pairs, respectively, a local data line pair provided common to the plurality of bit line pairs to transfer stored data with respect to an external source, a plurality of first connection circuits selectively connecting the plurality of bit line pairs to a local data line pair according to a column address, a plurality of data retain circuits provided corresponding to the plurality of bit line pairs, respectively, and a plurality of second connection circuits connecting the plurality of data retain circuits to the plurality of bit line pairs, respectively.
The block decode circuit selects any of the plurality of memory cell array blocks according to an applied row address. The select circuit transfers data with respect to any of the plurality of memory cell array blocks according to the output of the block decode circuit.
The select circuit includes a global data line pair provided common to the plurality of memory cell array blocks, a plurality of switch circuits provided corresponding to the plurality of memory cell array blocks, respectively, selectively connecting a local data line pair of the plurality of memory cell array blocks to a global data line pair, and a switch drive circuit rendering active any of the plurality of switch circuits according to an output of the block decode circuit.
The switch drive circuit includes a retain unit retaining the output of the block decode circuit.
Therefore, the main advantage of the present invention is that a readout address does not have to be specified when a write address and a read address are apart and reading and writing are repeated alternately to allow high speed operation, since a data retain circuit retaining data of a memory cell read out by a column select operation is provided.
Another advantage of the present invention is that, when there are a plurality of memory cell array blocks, high speed readout is allowed without addressing even when a block is to be selected by a row address since information of a memory cell array block corresponding to data stored in the data retain circuit is retained.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.